vishay siliconix SIP1759DB new product document number: 73784 s-61383?rev. a, 31-jul-06 www.vishay.com 1 100 ma buck-boost regulator demonstration board features ? sip1759 demonstration board includes the requi- red components to evaluate the ic's performance ? easy hook-up to demonstrate performance of the ic, stand alone or in a system ? charge pump based ic ? 100 ma output description the siliconix SIP1759DB demonstration board con- tains all the circuitry required to demonstrate the fully integrated buck-boost regulator. this demonstration board utilizes the adjustable output voltage version of the sip1759, while the fixed output version may be preferable in an actual application. applications ? 1-cell li ion battery powered equipment ? 2- to 3-cell nimh battery powered equipment ? 2- to 3-cell alkaline battery powered equipment ? backup battery boost converters in addition to allowing evaluation of the sip1759's per- formance, the layout shows the small amount of pc board area required for implementation. demonstration board hook up sh u t do w n j u mper inp u t s u pply (+) inp u t g n d to p v ie w error o u tp u t o u tp u t g n d scope pro b e g n d hook u p point bottom view
www.vishay.com 2 document number: 73784 s-61383?rev. a, 31-jul-06 vishay siliconix SIP1759DB schematic diagram demonstration board operation 1) to use the demo board, connect a 1.6 to 5.5 v power supply to the vin (tp3) & gnd (tp5) pins. 2) place a jumper between the center and en pin to enable the regulator's operation. connecting the center pin to the sd pin with disable or shut down the regulator. 3) a load resistor or electronic load should be con- nected to the v out (tp4) & gnd (tp6) pins in order to simulate typical loaded conditions for this type of circuit. bill of material item qty designator part type description footprint manufacturer 1 2 c1, c2 10 f cap, ceramic, 10 v 1206 vishay 2 1 c3 0.33 f cap, ceramic, 10 v 1206 vishay 3 1 r1 76.8 k res suface mount 1206 vishay/dale 4 1 r2 75 k res suface mount 1206 vishay/dale 5 1 r3 100 k res suface mount 1206 vishay/dale 6 1 u1 sip1759dh power ic msop-10 vishay/siliconix 7 6 tp1-6 test point 1 pin header tp1 multi-source
document number: 73784 s-61383?rev. a, 31-jul-06 www.vishay.com 3 vishay siliconix SIP1759DB choice of components output voltage the sip1759 regulated output is set at 2.5 v for ship- ment. it can be adjusted from 2.5 v to 5.5 v via resistor divider network from v out to gnd. r1 and r2 should be kept in the 50 k to 100 k range for low power consumption, while maintain ing adequate noise immu- nity. the value r1 is calculated using the following for- mula: r1 = r2((vout/vfb)-1) vfb is nominally 1.235 v. capacitor selection the value for the c in and c out capacitors is 10 f and the value of the c x capacitor is 0.33 f. capacitor selection for c in , c out and cx will have an impact on the voltage output ripple, output current and overall physical size of the circuit. ceramic capacitors are recommenced for their low esr, ( 20 m ), which will help keep the output volt- age ripple at a minimum. output voltage ripple the sip1759 automatically decides whether to be in step up mode or step down mode depending on the v in , v out and current load conditions, therefore the voltage output ripple will va ry. in step-up mode the voltage output ripple is higher than step-down mode. but unless v in is significant larger than v out (v in v out + 1 v), in heavy lo ad the ic will slip from buck mode to boost mode as necessary to charge the transfer capacitor and the ripple will increase. reduc- ing the c x capacitor value will caus e an increase in the swit-ching frequency and a reduction of the output rip- ple. printed circuit board top silk screen top layer bottom layer
www.vishay.com 4 document number: 73784 s-61383?rev. a, 31-jul-06 vishay siliconix SIP1759DB printed circuit board top solder mask mechanical bottom solder mask
document number: 73784 s-61383?rev. a, 31-jul-06 www.vishay.com 5 vishay siliconix SIP1759DB typical waveforms 5 s/div v in = 2.5 v v out = 3.3 v r load = 33 v out = 3.3 v 50 mv/div v c+ 50 v/div v in 50 mv/div 5 s/div v in = 4.2 v v out = 3.3 v r load = 33 v out = 3.3 v 50 mv/div v c+ 50 v/div v in 50 mv/div figure 1. typical switching waveform (v out > v in ) figure 2. typical switching waveform (v out < v in ) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 120 100 80 60 40 20 0 input voltage (v) efficiency (%) i out at 10 ma i out at 50 ma i out at 100 ma figure 3. efficiency vs. input voltage ordering information part number marking temperature range SIP1759DB SIP1759DB - 40 to 85 c
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